Experiment #04Experiment #04
I decided to run some tests on the phase stages circuits from Osamu Hoshuyama's great synth site: phasefet0205.gif.
I worked on circuits #1, #2 and #4, and on a variant of #2 which leaves the capacitor out (circuit #2+).
I used Cool Edit Pro to generate and loop a 600hz sine signal. This plays only on the right channel of the soundcard, which is connected to the circuit input. The output is hooked to the soundcard's left input, and this signal is analysed using Spectra Pro. The soundcard is an M-Audio Audiophile 2496.
The r value choosen was 100K, with a 100nF ceramic cap in #2. The trick was to use an inverter from a CD4069 CMOS chip as the N-MOSFET.
The circuits were adapted for single supply operation, which means the source of the MOSFET goes to Vref instead of ground.
I hooked a 50k trimpot to provide a variable bias voltage on the MOSFET's gate (Vgs).
The capacitor used for the phase stage was 470nf, to minimize its influence on the circuit behaviour.
The amplitude of the tone used for the THD tests was -5dBV rms (aprox. 500mV rms).
Click on the images to enlarge
In this circuit the distortion grows to a maximum and then drops. Of course, it drops probably because the MOSFET is off, so this is not usefull for modulation purposes. The remaining distortion is probably caused by the body diodes of the MOSFET.
It clearly shows the advantage of the linearization circuit, as the THD drops to about a 30%. But once you get to the max THD point, if you drop the bias a little more (or raise the signal level),
a discontinuity appears on the waveform, and the nature of the distortion changes abruptly.
It can be seen on the last graph. And this is how it looks like on the waveform:
I found no particular differences between circuit #2, #2+ and #4. All of them reduce the distortion by about the same amount, and also exhibit the discontinuity problem. Circuits #2+ and #4 introduce the disadvantage of having to readjust the bias, because of the DC connection between the drain and gate of the MOSFET.
On a real phaser I found pretty strong evidence of the slow tracking characteristic of circuit #2. I have yet to test that with circuits #2+ and 4 (which is supposed to be better)
What I also found is that, in terms of THD, dropping the Vgs has the same effect as raising the signal level. So you want to use this things at the higher bias posible, and with the lower signal you can.
On a real 4 stage phaser, using circuit #2, I had to use a 1/3 voltage divider before the stages to keep distortion at usable levels. This has the drawback of introducing a good amount of hiss.
I converted the stage to a voltage follower so I was able to measure the AC resistance of the MOSFET at various bias voltages.
The procedure was to put a known resistor before the + input, and to adjust the trimpot until the signal dropped exactly 6dB.
I was suprised to find the low values of the resistance, at least for low distortion bias voltages. And it is also pretty non-linear, so, as usual, the best LFO to use for this circuits for a linear sweep, is an hypertriangular one.
I put all my results on Excel to produce these graphics which summarize the findings:
Finally, I wouldn't take the numbers of these results as exact, as my setup is not really a laboratory. All the readings were made by Spectra Pro software, which was calibrated using a DMM, and no compensation was used.
As a reference point, in this setup my Gibson SG produces a signal that almost reaches -20dBV rms when hitting it really hard.
If you have comments, corrections or suggestions, please send me an email!
Good luck.
Miguel.
Miguel Canel, Buenos Aires, Argentina
bioroids.miguelNOSPAM@yahoo.com.ar (Quitar NOSPAM) http://www.bioroids.com.ar