Idea #02Idea #02
This LFO generates a stepped triangle waveform, like an up/down staircase. It can also go only up (or only down) for stepped ramp waveforms, and it can give other interesting patterns as well.
The CD4029 is a 4-bit CMOS counter with up/down capabilities and binary outputs.
The CD4013 is a dual Flip Flop. Half of it is used to generate the clock signal for the CD4029 (thanks Gez !) and make it count. The count direction is set by the output of the other half of
the CD4013, setted as a toggle and driven by the carry output of the CD4029. With the aid of Q5, a BC549 transistor, this makes the CD4029 count up from 0 to 15, then down to 0 again, ad infinitum.
Click on the image to enlarge
At the binary outputs of the CD4029, the network formed by diodes D4 to D7 and resistors R6 to R10 (ignore the switches for now) work as a rough digital-to-analog converter. A voltage proportional to the number represented by the counter appears at the anode of D3. The voltage will jump up and down following the count.
Q2 serves to buffer it and source a current proportional to this voltage at the modulation output.
It is assumed to be connected to a LM13600 or similar OTA Iabc input, wich looks like two diodes to ground. As an alternative, it can be connected to the LED of a LED/LDR combo, though I didn't tried this.
That's how we get the 16-steps triangle control current for our effect.
Then there's the Direction switch, SW1. This is a On-Off-On SPDT (the center position disconnects all lugs), wich controls the direction of the CD4029 counter (set by high/low state on pin 10).
When SW1 connects to the flip-flop toggle output (the net labeled Direction) the counter does the up/down thing described before. When connected to the other side (GND) the counter goes only down, and the output is a ramp-down waveform.
When the switch is at center, resistor R4 provides a conection to Vcc, wich causes the counter to go always up, for a ramp-up waveform.
Each of the counter binary outputs can be disabled by a SPST switch (SW2 to SW5). This gives a total of 16 combinations (one of them does nothing at all, and other is the standard traingle already described).
By disabling the least significant bit (SW5) the waveform is still the triangle, but with 8 steps instead of 16. Disabling SW5 and SW4 gives a 4-step triangle, and so on. Using only SW2 gives a square waveform.
Now, what happens if only SW2 is disconnected? The waveform is now obtained using the lower 3 bits of the counter. Assuming the triangle direction is selected, the count will do two ramps from 0 to 7, then two ramps from 7 to 0, on each cycle.
Other combinations give different patterns, and some may require to adjust the depth using P2, to compensate for the difference in voltage.
Capacitor C3 provides some filtering to smooth the steps, just to get rid of ticking noises. Some patterns may be noisier (in particular those with high voltage jumps like the ramp down) and require more filtering. Another cap can be added in parallel with a SPST switch.
Using a much bigger cap (like 10-22uf) gives a very smooth waveform for standard modulation. May need compensation at the Depth pot
As a side effect, the diode/resistor network that does the digital to analog conversion gives a slightly deformed triangle, resembling a little an hypertriangular wave.
This circuit runs on +5v power, wich can be provided by a simple 78L05 voltage regulator. This is used to avoid the LFO to behave differently as the battery voltage drops out.
Miguel Canel, Buenos Aires, Argentina
bioroids.miguelNOSPAM@yahoo.com.ar (Quitar NOSPAM) http://www.bioroids.com.ar